1. Field of the Invention
The present invention relates to a static random access memory unit. More particularly, the present invention relates to a single transistor static random access memory unit.
2. Description of the Related Art
With the fabrication of semiconductor devices having deep sub-micron dimension, the size of each device is also reduced even further. Consequently, the size of each memory cells in a memory device has become smaller and smaller. On the other hand, as the quantity of data that needs to be stored and processed inside our information electronic products (such as computers, mobile phones, digital cameras or personal digital assistant) continues to increase, the information electronic products demand memories with ever-increasing storage capacity. With such conflicting demands for a larger storage capacity but a shrinking size in the memory, methods capable of producing a smaller memory device, a higher integration level for the device and yet maintaining a certain high quality level is a major target for the industry.
Random access memory (RAM) is a versatile volatile memory widely used in many types of information electronic products. In general, RAM can be categorized as a static random access memory (SRAM) and dynamic random access memory (DRAM).
SRAM stores digital signals through the conductive state of the transistor inside a memory cells. According to the design method, each conventional SRAM memory cell is built using four transistors and two resistors (4T and 2R) or using six transistors (6T). On the other hand, DRAM stores digital signals through the charging state of the capacitor inside a memory cell. According to the design method, each conventional DRAM memory cell is built using a single transistor and a single capacitor (including a stacked capacitor or a deep-trench capacitor).
SRAM has a fast data processing speed and its production can be integrated with complementary metal oxide semiconductor (CMOS). Therefore, SRAM is simpler to fabricate. However, each memory cell in SRAM occupies a relatively large area (for the existing technology, area occupation of an SRAM memory cell having six transistors is roughly 10 to 16 times that of a DRAM memory cell) and hence provides very little leeway for significantly increasing the level of integration. On the other hand, although DRAM memory cells tend to occupy considerably less area than SRAM memory cells, the need for fabricating capacitors in a DRAM cell renders its fabrication more complicated and expensive.
In recent years, the industry has proposed a single transistor static random access memory (1T-SRAM or pseudo-SRAM). In the 1T-SRAM, a DRAM memory cell (1T1C) replaces the SRAM memory cell (6T or 4T2R) while the original peripheral circuit structure of the SRAM is still maintained. Hence, each memory cell can have a smaller dimension resulting in a higher level of integration and a lower random access cycling time. Moreover, there is no need to perform refreshing operations similar to a conventional SRAM. Thus, 1T-SRAM is an ideal candidate for replacing the conventional SRAM and DRAM.
Nevertheless, the memory units inside the memory cell array of a 1T-SRAM as currently developed by the industry is not optimally disposed. As a result, a lower level of integration is obtained.